Low-Resistance Buffer Layer That Paves the Way for Vertical GaN Devices on Silicon

In recent years, an increase in power consumption, owing in part to a rapid increase in the number of AI data centers, has become a major social problem. Moreover, for the widespread adoption of electric vehicles and micro-LEDs toward future decarbonization, “high-efficiency × low-cost” power conversion elements and light-emitting devices need to be mass-produced on a large scale. A key to achieving this goal will be to fabricate vertical GaN devices on low-cost Si wafers. In the past, however, vertical GaN devices could only be realized by using high-cost single-crystal GaN substrates, and there were challenges in terms of cost and productivity. When a low-cost Si wafer is used instead of a single-crystal GaN substrate, it becomes difficult to make the current flow vertically between the substrate and the GaN film due to the high resistance of the intermediate layer (buffer layer) formed between Si and GaN, and this hinders its application to vertical devices.

In this study, a research team from NIMS developed a novel technique to form a buffer layer (amorphous-like interlayer (AL-IL)) that facilitates the epitaxial growth of a GaN thin film on a Si wafer while realizing low-resistance vertical electric conduction at the GaN/Si interface.
As shown in Figure 1, this technique forms an ultra-thin amorphous-like interlayer (AL-IL) containing Si and N by forming a metal film with a thickness less than 1 nanometer (one-billionth of a meter) on a Si wafer, rapidly heating it, and then depositing GaN by sputtering. The team confirmed through transmission electron microscopy observation and other means that this intermediate layer accommodates the lattice mismatch between Si and GaN and enables the epitaxial growth of GaN. The team further demonstrated that a high-quality GaN film can be grown by depositing GaN by metalorganic chemical vapor deposition (MOCVD) using a sputtered GaN film as the platform. When current-voltage (I-V) characteristics were evaluated by forming electrodes between the GaN film and the Si substrate, it was found that the electric current flows in the vertical direction (the direction of the yellow arrow in the right diagram in Figure), exhibiting ideal current characteristics for device fabrication. This achievement fulfills one of the key requirements for realizing vertical GaN devices on Si wafers.

As vertical GaN devices on a Si wafer can make the electric current flow in three dimensions, they can increase the amount of current by several orders of magnitude compared to lateral devices that make the current flow in two dimensions (devices that make the current flow in the direction parallel to the substrate in the right diagram in Figure). Moreover, since vertical GaN devices enable the formation of electrodes on the back of the Si wafer, they can dramatically reduce the production cost. The realization of vertical GaN devices through this technique is expected to accelerate the widespread adoption of next-generation devices, including widespread use of micro-LED devices, reduction of power consumption at data centers, which are key facilities for AI technologies, and improvement of the energy efficiency of electric vehicles.

• This project was conducted as part of “Basic research for the realization of vertical GaN devices “ led by Fumio Kawamura (Principal Researcher, Ultra-wide Bandgap Semiconductors Group, Research Center for Electronic and Optical Materials, NIMS) and Kazutaka Mitsuishi (Deputy Director, Center for Basic Research on Materials, NIMS) under the Program of the Acquisition, Technology and Logistics Agency.
• This research result was published in Advanced Physics Research (open access) on May 29, 2026.