About Semiconductor Nano-integration Group
For the NEXT technologies of semiconductor nanomaterials and device integration on the silicon (Si) complimentary metal-oxide-semiconductor (CMOS) and complimentary field-effect transistor (CFET) platform beyond the “1-nm-process” in 2030s, our Semiconductor Nano-integration Group aims to the research and development of “the Best of Both Worlds”, i.e., top-down and bottom-up approaches, method for the integration of heterogeneous nanomaterials in semiconductor electronics. Our approach is based on the idea that it is NOT necessary to realize any integration technologies of semiconductor nanomaterials and devices on Si platform only by either of top-down or bottom-up fabrication methods.
The group is going to conduct the experiments for the application and creation of semiconductor nanoelectronic devices integrated heterogeneously on Si platform, in combination with the fundamental approaches for the fabrication of nanostructures and the characterization of their materials property.
Specialized Research Field
Integration Technologies for Semiconductor Nanomaterials only Created by Bottom-up Approach
Our novel bottom-up approach, i.e., the site-controlled growth by metal-organic vapor phase epitaxy (MOVPE) and chemical vapor deposition (CVD), enables us to create group III-V compound and group IV semiconductor nanostructures, e.g., vertical free-standing semiconductor nanowires, directly grown heterogeneously on Si wafers, which is not possible to be realized by the conventional top-down fabrication methods for thin-film semiconductors. These nanostructures can be grown at relatively high growth temperature, which is applicable only to the front-end-of-line (FEOL) of Si process and show novel nanoelectronic properties and crystallographic structures, which have not been shown in the bulk and thin films of semiconductors.
The aim of our group is to investigate and develop the heterogeneous integration methods on the Si platform, using the well-established surface activated bonding technology at room temperature, for these novel semiconductor nanomaterials only created by our bottom-up approach.
Semiconductor Nanomaterials Integration Technologies by “the Best of Both Worlds”: Top-down and Bottom-up Approaches
The middle-of-line (MOL) and back-end-of-line (BEOL) of Si process, on the other hand, need a relatively low growth temperature, e.g., < 400°C, for semiconductor nanomaterials. Based on the original bottom-up fabrication method developed for semiconductor heterogeneous nanomaterials by the group leader and others, our group is investigating and developing the direct site-controlled growth approaches for two-dimensional (2D) nanosheet channel materials, i.e., transition metal dichalcogenide (TMDC) etc., onto Si platform, e.g., so-called CFET, in the next generation.
The approach in our group presumably enables the semiconductor industry in the world to realize the heterogeneous integration of 2D-TMDC nanosheets site-controlled on the Si nanostructures of CFET by the top-down fabrication methods in Si nanoelectronics.
Group Members
