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Poster SM-04

Development of reconfigurable ternary logic-in-memory;
floating-gate-type organic antiambipolar transistor

Taiga Kijima

Author

Taiga Kijima1,2, Ryoma Hayakawa1,2, Yutaka Wakayama1

Affiliation

1Semiconductor Functional Device Group, MANA, NIMS
2Department of Applied Chemistry, Chuo University

URL

https://www.nims.go.jp/mana/research/semiconductor-materials/semiconductor-functional-device.html

Biography

Student / NIMS Graduate Research Assistant
Semiconductor Functional Device Group

Abstract

Organic integrated circuits (ICs) have attracted considerable attention for the applications in flexible and low-cost wearable electronics. However, their integration density remains limited due to their incompatibility with conventional lithography techniques. Multivalued logic (MVL) circuits are promising alternatives to conventional binary logic circuits because they could potentially realize low power consumption and high integration density by reducing the number of interconnects [1, 2].

Here, we demonstrated a reconfigurable ternary logic-in-memory (LIM) circuit consisting of only two transistors: organic antiambipolar transistor (OAAT) and n-type transistor (Fig. 1). The gold floating gate (FG) sandwiched between two HfO2 layers enabled three distinct ternary inverter operations. First, standard ternary inverter (STI) operation with a high static noise margin was demonstrated at a low operating voltage of 2 V (Fig. 2). Furthermore, hole or electron storage in the FG induced a lateral shift of up to 1.8 V in the voltage transfer curve, resulted in a nonvolatile memory window. This memory effect enables reconfigurable ternary inverter operation, where STI, negative ternary inverter (NTI) and positive ternary inverter (PTI) operations could be electrically selected under the same input voltages (Fig. 3). These results can significantly improve the information density of organic ICs and provides a promising pathway toward a new computing architecture that could alleviate the von Neumann bottleneck.

Device structure of ternary LIM with Au floating gate
Fig. 1. Device structure of ternary LIM with Au floating gate. PhC2-BQQDI and Ph-BTBT-C10 films are used as transistor channels.
Vout–Vin curves at initial, hole-trapped, and electron-trapped states
Fig. 2. Vout–Vin curves obtained at initial (black line), hole-trapped (red line), and electron-trapped (blue line) states. Reprinted from [Ref. 3] with permission (copyright 2026, Wiley-VCH GmbH).
Reconfigurable ternary inverter operations
Fig. 3. Reconfigurable ternary inverter operations: (i) STI (initial state), (ii) PTI (electron-trapped state), and (iii) NTI (hole-trapped state). Reprinted from [Ref. 3] with permission (copyright 2026, Wiley-VCH GmbH).

References

  1. Y. Wakayama, R. Hayakawa, Adv. Funct. Mater. 30, 1903724 (2019). DOI: 10. 1002/adfm.201903724
  2. K. Kobashi et al., Nano Lett. 18, 4355 (2018). DOI: 10.1021/acs.nanolett.8b01357
  3. R. Hayakawa et al., Adv. Electron. Mater. e70538. (2026). DOI: 10.1002/aelm.70538
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