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Poster SM-03

Development of Two-Dimensional-Material-based Anti-Ambipolar Transistor Using Laser Patterning

Aoto Igarashi

Author

Aoto Igarashi1,2, Ryosuke Imura1,2, Kentaro Uzawa2, Ryoma Hayakawa1, Takuya Iwasaki3, Kenji Watanabe4, Takashi Taniguchi5, Takeo Minari6, Yasumitsu Miyata7, Takahiko Endo7, Satoshi Moriyama2, Yutaka Wakayama1,2

Affiliation

1Semiconductor Functional Device Group, MANA, NIMS
2Tokyo Denki Univ

URL

https://www.nims.go.jp/mana/research/semiconductor-materials/semiconductor-functional-device.html

Biography

Student/NIMS Graduate Research Assistant
Semiconductor Functional Device group

Abstract

An anti-ambipolar transistor (AAT) is a heterojunction transistor composed of p- and n-type semiconductors that exhibits negative differential transconductance (NDT). This unique transport characteristic enables the realization of advanced logic circuits, including multivalued and reconfigurable logic circuits. In this study, we prepared an AAT based on two-dimensional (2D) materials, where MoS₂ and WSe₂ thin films grown on sapphire substrates by chemical vapor deposition (CVD) were utilized as the n- and p-type transistor channels, respectively. Importantly, these films were precisely patterned using a Nd: YAG laser. Although mechanical exfoliation techniques are widely used to form 2D-material-based transistors, variations in flake size and thickness limit device-to-device reproducibility and large-scale integration.
 Figure 1(a) shows a schematic illustration and an optical microscope image of the prepared AAT. In this device, Au electrode and HfO₂ layer behave as the bottom gate and gate insulating layer, respectively. A hexagonal boron nitride (h-BN) film was dry-transferred onto the HfO₂ layer to passivate interfacial defects. The CVD-grown MoS₂ and WSe₂ films were then sequentially transferred onto the h-BN/HfO₂ layer to form a MoS₂/WSe₂ heterointerface. The channel region centered around the heterointerface was patterned into a 5 × 15 μm size using Nd:YAG laser with a wavelength of 532 nm. In/Au and MoO₃/Au were used as source/drain electrodes for the MoS₂ and WSe₂ channels, respectively.
 Figure 1(b) indicates the drain current (ID)–gate voltage (VG) curve of the prepared AAT measured under vacuum. At a fixed drain voltage (VD) of VD = 5.0 V, the gate voltage VG was swept from −5 to 5 V. ID started increasing at VG (VON) = −0.8 V and reached a peak ID (IPeak) of 1.5 nA at VG (Vpeak) = 0.6V. Subsequently, ID decreased with increasing VG and was completely suppressed at VG (VOFF) = 1.7 V and reached a Valley ID (IValley) of 29.6 pA. The PVR, which is the ratio of IPeak to IValley, was calculated as 52. These results exhibit typical NDT behavior. As described above, the proposed formation method provides a promising platform for reproducible 2D-material-based AATs and their integration into functional circuits, including applications in multivalued logic circuits in future.

Figure for Aoto Igarashi abstract
Fig.1 (a) Device structure and optical microscope image of the AAT. (b) ID–VG curve of the prepared AAT obtained at VD =5.0 V
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