Dr. Yao-Jen Lee is a Professor at the Institute of Pioneer Semiconductor Innovation, National Yang Ming Chiao Tung University (NYCU), where he leads the Advanced Stacked Device Laboratory. He also serves as an Adjunct Research Fellow at the Taiwan Semiconductor Research Institute (TSRI), where he previously spent 16 years conducting research on advanced semiconductor devices and process technologies. His research focuses on advanced semiconductor devices and three-dimensional integration, including microwave annealing, Si/SiGe/Ge CFETs, oxide semiconductor FETs based on SnO, IGZO, and In₂O₃, vertically stacked transistors, and cryogenic Si/Ge devices. His group is currently developing multi-tier gate-all-around oxide semiconductor devices for high-performance logic and monolithic three-dimensional integration.

Continued CMOS scaling requires simultaneous advances in channel materials, device architecture, and vertical integration [1]. This talk presents our recent progress in germanium (Ge) CMOS process integration and back-end-of-line (BEOL)-compatible transistors for future three-dimensional systems. The first part focuses on Ge technologies spanning material preparation, interface engineering, source/drain activation, contact formation, and device integration [2]. Ge-on-insulator FinFETs and gate-all-around nanosheet devices are used to examine how surface chemistry, thermal budget, parasitic resistance, and low-temperature operation [3]. To increase functional density, low-temperature layer transfer and bonding are further combined with vertically stacked n- and p-channel devices, enabling heterogeneous Ge/Si complementary FETs and multi-nanosheet Ge CFETs, as shwon in Fig. 1. The second part addresses BEOL-compatible device integration using oxide semiconductors. Vertically stacked oxide-semiconductor gate-all-around transistors provide a pathway to add logic or memory functions above completed CMOS while maintaining a restricted thermal budget [4]. We compare source/drain contact schemes, including conventional sidewall contacts and metal-interlayer-assisted structures, and discuss their tradeoffs in process complexity, contact resistance, footprint, and scalability, as shwon in Fig. 2. Across both Ge and oxide-semiconductor platforms, the central theme is the co-optimization of materials, interfaces, contacts, and three-dimensional architecture. These results outline a process route from high-mobility Ge CMOS to sequentially integrated BEOL electronics, while identifying remaining challenges in variability, thermal compatibility, reliability, and system-level interconnection. The presentation concludes with opportunities for combining these platforms in integrated logic, memory, and cryogenic applications.

1. W. Cao, H. Bu, M. Vinet, M. Cao, S. Takagi, S. Hwang, T. Ghani, and K. Banerjee, Nature 620(7974), 501–515 (2023), DOI: 10.1038/s41586-023-06145-x.
2. R. Pillarisetty, Nature 479(7373), 324–328 (2011), DOI: 10.1038/nature10678.
3. X. R. Yu, J. Y. Hung, T. C. Cho, W. C. Y. Ma, Y. J. Lee, and Y. H. Wang, IEEE Transactions on Electron Devices 72(4), 1597–1603 (2025), DOI: 10.1109/TED.2025.3545401.
4. W. H. Lu, Y. H. Yeh, C. T. Chen, W. H. Chang, T. Maeda, Y. J. Lee, and Y. H. Wang, IEEE Electron Device Letters 47(3), 621–624 (2026), DOI: 10.1109/LED.2026.3655893.