Tzu-Ting Weng is a Ph.D. candidate in institute of Electronics at National Yang Ming Chiao Tung University, working under Prof. Der-Hsien Lien, with a current collaborative research stay at NIMS WPI-MANA under the guidance of Dr. Kazuhito Tsukagoshi. Her research, developed in collaboration between the two groups, focuses on low-temperature oxide semiconductor fabrication, tellurium-based p-type devices, and monolithic 3D integration technologies for post-CMOS computing hardware applications.

Monolithic three-dimensional (M3D) integration has emerged as a promising strategy for extending device scaling beyond the constraints of conventional planar architectures. By vertically integrating multiple device layers through fine-pitch interconnects, M3D technology can increase functional density while reducing interconnect length and energy consumption in advanced logic and memory systems. A major challenge, however, is the stringent back-end-of-line (BEOL) thermal constraint, as post-fabrication processes must remain below approximately 400 °C to avoid damaging the underlying circuitry. Although various low-temperature semiconductor materials have been explored for M3D applications, few can support complementary n- and p-type devices with sufficient flexibility for arbitrary vertical stacking. In this work, we demonstrate a complementary field-effect transistor (CFET) platform based on low-temperature-deposited n-type indium oxide (In₂O₃) and p-type tellurium (Te). The proposed reversible stacking approach allows the realization of CMOS inverters, multilayer logic circuits, and a functional three-dimensional SRAM cell. Importantly, the entire fabrication process is completed below 300 °C, making the platform compatible with BEOL processing. This approach establishes a scalable route toward vertically integrated complementary electronics with built-in interconnectivity, offering new opportunities for future three-dimensional system-on-chip architectures.

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