MANA International Symposium 2026

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Session 3-2

Materials and Device Technology Development Using a 300 mm Pilot Line for Si Nanosheet Gate-All-Around Transistors

Toshifumi Irisawa

Author

Toshifumi Irisawa

Affiliation

AIST

URL

https://unit.aist.go.jp/sfrc/index_en.html

Biography

Toshifumi Irisawa is a team leader of Device Process Research Team at Semiconductor Frontier Research Center (SFRC) in National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Japan. He received B.S., M.S., and Ph.D. degrees in applied physics from The University of Tokyo, Tokyo, Japan, in 1998, 2000, and 2003, respectively. From 2003 to 2015, he was with Toshiba Research and Development Center. In 2015, he joined AIST. He has been working on advanced transistor technologies using novel device structures and channel materials.

Abstract

Research and development of CMOS transistor technologies for the 2 nm technology node and beyond is rapidly accelerating. In this scaling regime, Si nanosheet gate-all-around field-effect transistors (NS-GAAFETs), featuring channel thicknesses below 10 nm, are expected to replace conventional FinFETs owing to their superior electrostatic controllability and larger drive current per unit footprint. To realize high-performance and low-power GAAFETs, several key process and integration challenges must be addressed, including the formation of thin and uniform Si NSs through Si/SiGe epitaxy, the fabrication of scaled high-k/metal gate stacks with precisely controlled threshold voltage in the narrow spaces between stacked Si NSs, the formation of low-resistance source/drain regions by heavily doped selective epitaxy, and their seamless integration into a practical CMOS process flow. To address these challenges, AIST has established a 300 mm wafer platform [1], and intensive research and development of Si-NS GAAFETs is being conducted using this platform [2-7].

Fig. 1. Cross sectional TEM image of Si-NS GAAFET fabricated in AIST 300-mm wafer platform [1].
Fig. 1. Cross sectional TEM image of Si-NS GAAFET fabricated in AIST 300-mm wafer platform [1].
Fig. 2. Electrical characteristics of Si-NS GAAFET fabricated in AIST 300-mm wafer platform [1].
Fig. 2. Electrical characteristics of Si-NS GAAFET fabricated in AIST 300-mm wafer platform [1].

References

  1. AIST press release, Nov. 5th (2025). https://www.aist.go.jp/aist_j/press_release/pr2025/pr20251105/pr20251105.html
  2. K. Uejima et al., IEEE Electron Devices Technology & Manufacturing Conference (EDTM) (2026). DOI:10.1109/EDTM65772.2026.11496736
  3. K. Uejima et al., International Conference on Solid State Devices and Materials (SSDM), A-5-02 (2026).
  4. H. Ota et al., International Conference on Solid State Devices and Materials (SSDM), A-2-03(2025). https://doi.org/10.7567/SSDM.2025.A-2-03
  5. N. Kumagai et al., International Conference on Silicon Epitaxy and International SiGe Technology and Device Meeting (ICSI/ISTDM), pp. 189 (2025).
  6. N. Kumagai et al., International Conference on Solid State Devices and Materials (SSDM), A-1-03 (2026).
  7. R. Nishino et al., International Conference on Solid State Devices and Materials (SSDM), A-3-01 (2026).
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