MOCVD-Grown MoS2 Wafers as a Transfer-Free Platform
for Top-Gate Devices
Author
Kosuke Nagashio
Affiliation
The University of Tokyo
URL
Biography
Kosuke Nagashio received Ph.D. degrees in Materials Engineering from The University of Tokyo in 2002. From 2002 to 2003, he was a postdoctoral research fellow at Stanford University, California. He is currently a Professor with the Department of Materials Engineering, The University of Tokyo. His current research interests include the growth, characterization, device fabrication, and electronic transport properties of two-dimensional materials and related systems.
Abstract
We elucidate the electronic origin of hidden interfacial doping in monolayer MoS2 single-crystal wafers grown on sapphire by metal–organic chemical vapor deposition (MOCVD) and establish a transfer-free top-gate device platform. Despite structural perfection, as-fabricated devices exhibit degenerate electron doping and lack a clear off state. Hall measurements quantify an interfacial electron density of 2.7×1012 cm−2, evidencing substantial charge transfer across the nominal van der Waals interface. Interface-sensitive spectroscopy, lateral force microscopy, and thermal desorption analysis reveal a buried sulfate-derived layer accompanied by a water-like interfacial structure that acts as an intrinsic electron donor. A purely dry H2/Ar annealing process selectively removes these species, suppressing charge transfer and restoring intrinsic FET characteristics without transfer or wet processing. Through this dry interface engineering approach, we demonstrate MOCVD-grown single-crystal MoS2 wafers as a robust, transfer-free platform for the reliable evaluation of intrinsic gate stacks and device performance.
References
- Y. Sakuma, and K. Nagashio, et al., “Self-aligned and self-limiting van der Waals epitaxy of monolayer MoS2 for scalable 2D electronics,” Nature Commun., 2026, 12, 602. DOI: 10.1038/s41467-026-68320-8
- S. Li, and K. Nagashio, et al., “MOCVD-Grown MoS2 Wafers as a Transfer-Free Platform for Top-Gate Devices via Dry Interface Engineering,” Adv. Mater. 2026, e73931. DOI: 10.1002/adma.73931