Electrical Properties of SiC MIS Structures Fabricated by SiN Deposition and CO2 Annealing
Author
Hisahiro Itoi, Takuji Hosoi
Affiliation
Semiconductor Device Group, MANA, NIMS
URL
Abstract
In SiC MOSFETs, low channel mobility caused by defects at the SiO2/SiC interface remains a critical issue. While post-oxidation annealing in NO is commonly used to improve interface properties,[1] concerns remain regarding reliability degradation associated with the progression of nitridation.[2] Furthermore, it has been reported that surface conditioning of SiC, including the removal of native oxide residues, plays a crucial role in determining the resulting MOS interface quality.[3,4] Therefore, in this study, as an oxidation-free approach, we propose a fabrication process for SiC MIS structures based on direct deposition of an SiN film using N2-based PECVD, and subsequent CO2 annealing.
Samples were prepared by depositing 20-nm-thick SiN films onto a 4H-SiC(0001) substrate, with optional CF4 plasma pre-treatment. For comparison, a control sample with a deposited SiO2 film was also prepared, and all samples were subjected to CO2 annealing at 1100ºC for 30 min. Electrical characterization revealed that the SiN-deposited samples processed via CO2 annealing exhibited steeper capacitance-voltage (C-V) characteristics (Fig. 1) and significantly lower interface state densities (Dit) compared to the SiO2-deposited controls, with CF4 plasma pre-treatment providing further improvement (Fig. 2), confirming the successful formation of a high-quality SiON/SiC interface.
References
- G. Y. Chung et al., IEEE Electron Dev. Lett. 22, 176 (2001), DOI: 10.1109/55.915604
- J. Rozen et al., J. Appl. Phys. 105, 124506 (2009), DOI: 10.1063/1.3131845
- K. Tachiki et al., Appl. Phys. Express 14, 031001 (2021), DOI: 10.35848/1882-0786/abdcd9
- T. Kobayashi et al., Appl. Phys. Express 18, 081002 (2025), DOI: 10.35848/1882-0786/adf6ff




